Facilitating Academic Research with FPGA Support in a University Data Center

Volume 16, Issue 2 (November 2025), pp. 22–28

Download PDF

@article{jocse-16-2-5,
  author={Jeevesh Choudhury and Thomas Jennewein and Gil Speyer},
  title={Facilitating Academic Research with FPGA Support in a University Data Center},
  journal={The Journal of Computational Science Education},
  year=2025,
  month=nov,
  volume=16,
  issue=2,
  pages={22--28},
  doi={https://doi.org/10.22369/issn.2153-4136/16/2/5}
}

Field Programmable Gate Arrays (FPGAs) offer a practical solution that balances computational power with energy efficiency, which could address the growing demand for sustainable high-performance computing (HPC). Moreover, because they can be reconfigured and optimized for specific applications, FPGAs open up numerous possibilities for adaptive, high-performance workloads. However, the substantial expertise required to deploy FPGA designs has traditionally been daunting, requiring proficiency in Hardware Description Languages (HDL) such as SystemVerilog or VHDL. To address this accessibility barrier, the field has shifted toward high-level synthesis (HLS), which allows developers to program FPGAs using familiar languages like C++ and Python---mirroring the evolution seen in GPU programming.<r> In this paper, the resources available on the Sol HPC cluster at Arizona State University (ASU) and the strategies employed to support and encourage researchers and instructors working with these nodes are examined. The practical challenges of using FPGAs, the integration of tools and libraries in the development workflow, and efforts to lower the expertise threshold required for effective use are explored. By sharing this experience, the aim is to contribute to the growing body of knowledge around accessible and sustainable FPGA development in HPC environments.