Enhancing HPC Education and Workflows with Novel Computing Architectures

Jeffrey Young, Aaron Jezghani, Jeffrey Valdez, Sam Jijina, Xueyang Liu, Michael D. Weiner, Will Powell, and Semir Sarajlic

Volume 13, Issue 2 (December 2022), pp. 31–38


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  author={Jeffrey Young and Aaron Jezghani and Jeffrey Valdez and Sam Jijina and Xueyang Liu and Michael D. Weiner and Will Powell and Semir Sarajlic},
  title={Enhancing HPC Education and Workflows with Novel Computing Architectures},
  journal={The Journal of Computational Science Education},
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Recent HPC education efforts have focused on maximizing the usage of traditional- and cloud-based computing infrastructures that primarily support CPU or GPU hardware. However, recent innovations in CPU architectures from Arm and RISC-V and the acquisition of Field-Programmable Gate Array (FPGA) companies by vendors like Intel and AMD mean that traditional HPC clusters are rapidly becoming more heterogeneous. This work investigates one such example deployed at Georgia Tech – a joint workflow for processor design and reconfigurable computing courses supported by both the HPC-focused Partnership for an Advanced Computing Environment (PACE) and GT's novel architecture center, CRNCH. This collaborative workflow of HPC nodes and 40 remotely accessible Pynq devices supported over 100 students in Spring 2022, and its deployment provides key lessons on sticking points and opportunities for combined HPC and novel architecture workflows.